1. Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having strained transistors and its manufacture method.
2. Description of the Related Art
Micro patterning is progressing in order to improve the integration density and operation speed of a silicon semiconductor integrated circuit. As miniaturization advances, the gate length of a field effect transistor is shortened. At a gate length of 65 nm or shorter, there appears a limit in expecting the performance improvements through miniaturization.
Apart from miniaturization, strained transistors which improve the mobility of carriers by strain have been paid attention as a technique of improving the performance of a field effect transistor. Strain is generated in the channel region of a field effect transistor to increase the mobility of electrons or holes and improve the on-current characteristics.
Field effect transistors are classified by the gate electrode structure into junction type that a channel is controlled by a pn junction, MOS type that a channel is controlled from a gate electrode via an insulating film such as an oxide film, and MIS type that a channel is controlled by a Schottky gate electrode. The following description will be made by taking as an example the MOS type using a Si substrate. Mobility of electrons of an n-channel (N) MOS transistor is improved by tensile stress and a mobility of holes of a p-channel (P) MOS transistor is improved by compressive stress, along the channel length (gate length) direction.
If the source/drain regions of an NMOS transistor are made of silicon-carbon (Si—C) mixed crystals having a lattice constant smaller than that of a Si substrate, tensile stress is applied to Si crystals in the channel along the channel length direction, so that electron mobility is increased (Refer to K. Ang et al: IEDM Tech. Dig., 2004, p. 1069).
If the source/drain regions of a PMOS transistor are made of by silicon-germanium (Si—Ge) mixed crystals having a lattice constant larger than that of a Si substrate, compressive stress is applied to Si crystals in the channel along the channel length direction, so that hole mobility is increased (Refer to T. Ghani et al: IEDM Tech. Dig., 2003, p. 978 and Y. S. Kim et al: Proceedings of ESSDERC 2005, p. 305).
Apart from the strained transistor, a channeling phenomenon is known wherein as impurity ions are implanted into Si crystals, some impurity ions are implanted deeply. In order to prevent the channeling phenomenon, there is a proposal to grow Si—C or Si—Ge in a single-crystal state having a high dislocation density or in a polycrystalline state, on source/drain regions, grow an Si film thereon and then implant impurity ions (Refer to Japanese Patent Laid-open Publication No. JP-A-2001-24194).
Various techniques have been proposed to form a shallow junction in source/drain regions. In one proposal, an undoped silicide layer is formed on source/drain regions, a doped dielectric layer is vapor-deposited on the silicide layer, impurities in the dielectric layer are diffused into the silicide layer by pulse laser annealing, impurities in the silicide layer are moved by annealing to form a junction having a depth of 100 nm or shallower. It is described that the source/drain regions are made of silicon, silicon-germanium, silicon carbide, or gallium arsenide (Refer to PCT National Publication No. HEI-11-506567).